Diodes AP6502A - Manual (Page 7)

AP6502A
Document number: DS35812 Rev. 3 - 2
7 of 14
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December 2012
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AP6502A
Application Information
Theory of Operation
The AP6502A is a 2A current mode control, synchronous buck regulator with built in power MOSFETs. Current mode control assures excellent
line and load regulation and a wide loop bandwidth for fast response to load transients. Figure 3 depicts the functional block diagram of
AP6502A.
The operation of one switching cycle can be explained as follows. At the beginning of each cycle, HS (high-side) MOSFET is off. The error
amplifier (EA) output voltage is higher than the current sense amplifier output, and the current comparator’s output is low. The rising edge of the
240kHz oscillator clock signal sets the RS Flip-Flop. Its output turns on HS MOSFET. The current sense amplifier is reset for every switching
cycle.
When the HS MOSFET is on, inductor current starts to increase. The current sense amplifier senses and amplifies the inductor current. Since
the current mode control is subject to sub-harmonic oscillations that peak at half the switching frequency, ramp slope compensation is utilized.
This will help to stabilize the power supply. This ramp compensation is summed to the current sense amplifier output and compared to the error
amplifier output by the PWM comparator. When the sum of the current sense amplifier output and the slope compensation signal exceeds the
EA output voltage, the RS Flip-Flop is reset and HS MOSFET is turned off.
For one whole cycle, if the sum of the current sense amplifier output and the slope compensation signal does not exceed the EA output, then the
falling edge of the oscillator clock resets the Flip-Flop. The output of the error amplifier increases when feedback voltage (V
FB
) is lower than the
reference voltage of 0.925V. This also increases the inductor current as it is proportional to the EA voltage.
If in one cycle the current in the power MOSFET does not reach the COMP set current value, the power MOSFET will be forced to turn off. When
the HS MOSFET turns off, the synchronous LS MOSFET turns on until the next clock cycle begins. There is a “dead time” between the HS turn
off and LS turn on that prevents the switches from “shooting through” from the input supply to ground.
The voltage loop is compensated through an internal transconductance amplifier and can be adjusted through the external compensation
components.
Enable
Above the ‘EN Rising Threshold’, the internal regulator is turned on and the quiescent current can be measured above this threshold. The enable
(EN) input allows the user to control turning on or off the regulator. To enable the AP6502A, EN must be pulled above the ‘EN Lockout Threshold
Voltage’ and to disable the AP6502A, EN must be pulled below ‘EN Lockout Threshold Voltage - EN Lockout Hysteresis’ (2.2V - 0.22V = 1.98V).
External Soft Start
Soft start is traditionally implemented to prevent the excess inrush current. This in turn prevents the converter output voltage from overshooting
when it reaches regulation. The AP6502A has an internal current source with a soft start capacitor to ramp the reference voltage from 0V to
0.925V. The soft start current is 6µA. The soft start sequence is reset when there is a Thermal Shutdown, Under Voltage Lockout (UVLO) or
when the part is disabled using the EN pin.
External Soft Start can be calculated from the formula below:
DT
DV
* C SS I
=
Where;
I
SS
= Soft Start Current
C = External Capacitor
DV = change in feedback voltage from 0V to maximum voltage
DT = Soft Start Time
Current Limit Protection
In order to reduce the total power dissipation and to protect the application, AP6502A has cycle-by-cycle current limiting implementation. The
voltage drop across the internal high-side MOSFET is sensed and compared with the internally set current limit threshold. This voltage drop is
sensed at about 30ns after the HS turns on. When the peak inductor current exceeds the set current limit threshold, current limit protection is
activated. During this time the feedback voltage (V
FB
) drops down. When the voltage at the FB pin reaches 0.3V, the internal oscillator shifts the
frequency from the normal operating frequency of 240kHz to a fold-back frequency of 80kHz. The current limit is reduced to 70% of nominal
current limit when the part is operating at 80kHz. This low fold-back frequency prevents runaway current.