Diodes AP7175 - Manual (Page 9)

AP7175
Document number: DS35606 Rev. 3 - 2
9 of 14
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December 2012
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UC
T
AP7175
Application Information
Power Good and Delay
AP7175 monitors the feedback voltage V FB on the FB pin. An internal delay timer is started after the PG voltage threshold (V THPG ) on the FB pin
is reached. At the end of the delay time an internal NMOS of the PG is turned off to indicate that the power at the output is good (PG). This
monitoring function is continued during operation and if V
FB
falls 8% (typ) below V
THPG
, the NMOS of the PG is turned on after a delay time of
typical 10µs to avoid oscillating of the PG signal.
Power On Reset
AP7175 monitors both supply voltages, V
CNTL
and V
IN
to ensure operation as intended. A Soft-Start process is initiated after both voltages
exceed their POR threshold during power on. During operation the POR component continues to monitor the supply voltage and pulls the PG low
to indicate an out of regulation supply. This function will engage without regard to the status of the output.
Soft-Start
AP7175 incorporates an internal Soft-Start function. The output voltage rise is controlled to limit the current surge during start-up. The typical
Soft-Start time is 0.6ms.
Current-Limit Protection
AP7175 monitors the current flow through the NMOS and limits the maximum current to avoid damage to the load and AP7175 during overload
conditions.
Short Circuit Current-Limit Protection
AP7175 incorporates a current limit function to reduce the maximum current to 1.1A (typ) when the voltage at FB falls below 0.2V (typ) during an
overload or short circuit situation.
During start-up period, this function is disabled to ensure successful heavy load start-up.
Enable Control
If the enable pin (EN) is left open, an internal current source of ~5µA pulls the pin up and enables the AP7175. This will reduce the bill of material
saving an external pull up resistor. Driving the enable pin low disables the device. Driving the pin high subsequently initiates a new Soft-Start
cycle.
Output Voltage Regulation
Output Voltage is set by resistor divider from V
OUT
via FB pin to GND. Internally V
FB
is compared to a 0.8V temperature compensated reference
voltage and the NMOS pass element regulates the output voltage while delivering current from V
IN
to V
OUT
.
Setting the Output Voltage
A resistor divider connected to FB pin programs the output voltage.
V
2 R
1 R
1 * V V
REF OUT
⎟
⎠
⎞
⎜
⎝
⎛ +
=
R1 is connected from V
OUT
to FB with Kelvin sensing connection. R2 is connected from FB to GND. To improve load transient response and
stability, a bypass capacitor can be connected in parallel with R1. (optional in typical application circuit)
Power Sequencing
AP7175 requires no specific sequencing between V
IN
and V
CNTL
. However, care should be taken to avoid forcing V
OUT
for prolonged times
without the presence of V
IN
. Conduction through internal parasitic diode (from V
OUT
to V
IN
) could damage AP7175.
Thermal Shutdown
The PCB layout and power requirements for AP7175 under normal operation condition should allow enough cooling to restrict the junction
temperature to +125°C. The packages for AP7175 have an exposed PAD to support this. These packages provide better connection to the PCB
and thermal performance. Refer to the layout considerations.
If AP7175 junction temperature reaches +170°C a thermal protection block disables the NMOS pass element and lets the part cool down. After
its junction temperature drops by 50°C (typ), a new Soft-Start cycle will be initiated. A new thermal protection will start, if the load or ambient
conditions continue to raise the junction temperature to +170°C. This cycle will repeat until normal operation temperature is maintained again.