Pam3102, Application information – Diodes PAM3102 User Manual
Page 9
PAM3102
Document number: DSxxxxx Rev. 1 - 2
9 of 12
July 2013
© Diodes Incorporated
PAM3102
A Product Line of
Diodes Incorporated
Application Information
Capacitor Selection and Regulator Stability
Similar to any low dropout regulator, the external capacitors used with the PAM3102 must be carefully selected for regulator stability and
performance.
A capacitor C
IN
of more than 1
μF can be employed in the input pin, while there is no upper limit for the capacitance of C
IN
. Please note that the
distance between C
IN
and the input pin of the PAM3102 should not exceed 0.5 inch. Ceramic capacitors are suitable for the PAM3102.
Capacitors with larger values and lower ESR (equivalent series resistance) provide better PSRR and line-transient response.
The PAM3102 is designed specifically to work with low ESR ceramic output capacitors in order to save space and improve performance. Using
an output ceramic capacitor whose value is >2.2µF with ESR>5m
Ω ensures stablilty.
Shutdown Input Operation
The PAM3102 is shutdown by pulling the CE input low, and turned on by tying the CE input to V
IN
or leaving the CE input floating.
Input-Output (Dropout) Voltage
A regulator's minimum input-output voltage differential (or dropout voltage) determines the lowest usable supply voltage. The PAM3102 has a
typical 180mV dropout voltage. In batterypowered systems, this will determine the useful end-of-life battery voltage.
Current Limit and Short Circuit Protection
The PAM3102 features a current limit, which monitors and controls the gate voltage of the pass transistor. The output current can be limited to
300mA by regulating the gate voltage. The PAM3102 also has a built-in short circuit current limit.
Thermal Considerations
Thermal protection limits power dissipation in the PAM3102. When the junction temperature exceeds 150°C, the OTP (Over Temperature
Protection) starts the thermal shutdown and turns the pass transistor off. The pass transistor resumes operation after the junction temperature
drops below 120°C.
For continuous operation, the junction temperature should be maintained below 125°C. The power dissipation is defined as:
I
*
V
I
*
V
V
P
GND
IN
O
O
IN
D
The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surrounding airflow and temperature
difference between junction and ambient. The maximum power dissipation can be calculated by the following formula:
JA
A
)
MAX
(
J
)
MAX
(
D
/
T
T
P
Where T
J(MAX)
is the maximum allowable junction temperature +125°C , T
A
is the ambient temperature and
θ
JA
is the thermal resistance from the
junction to the ambient.
For example, as is 250°C/W for the SOT-23 package based on the standard JEDEC 51-3 for a single-layer thermal test board, the maximum
power dissipation at T
A
=25°C can be calculated by following formula:
W
4
.
0
250
/
C
25
C
125
P
)
MAX
(
D
SOT-23
It is also useful to calculate the junction temperature of the PAM3102 under a set of specific conditions. Suppose the input voltage V
IN
= 3.3V,
the output current I
O
= 300mA and the case temperature T
A
= +40°C measured by a thermal couple during operation, the power dissipation is
defined as:
mW
300
A
200
*
V
3
.
3
mA
150
*
)
V
8
.
1
V
3
.
3
(
mA
150
*
V
8
.
2
V
3
.
3
P
D
And the junction temperature T
J
can be calculated as follows:
T
J
= T
A
+ P
D
*
θ
JA
T
J
= 40°C +0.3W*250°C/W
=40°C + 75°C
=115°C<T
J(MAX)
= +125°C
For this application, T
J
is lower than the absolute maximum operating junction temperature,+125°C, so it is safe to use the PAM3102 in this
configuration.