Pam8001, Application information – Diodes PAM8001 User Manual
Page 13
PAM8001
Document number: DSxxxxx Rev. 1 - 0
13 of 17
February 2013
© Diodes Incorporated
PAM8001
A Product Line of
Diodes Incorporated
Application Information
(cont.)
How to Reduce EMI (Electro Magnetic Interference)
A simple solution is to put an additional capacitor 1000uF at power supply terminal for power line coupling if the traces from amplifier to
speakers are short (<20CM).
Most applications require a ferrite bead filter as shown at Figure 1. The ferrite filter reduces EMI around 1 MHz and higher. When selecting a
ferrite bead, choose one with high impedance at high frequencies, and low impedance at low frequencies (MH2012HM221-T).
Figure 1 Ferrite Bead Filter to Reduce EMI
PCB Layout Guidelines Grounding
At this stage it is paramount to notice the necessity of separate grounds. Noise currents in the output power stage need to be returned to output
noise ground and nowhere else. Were these currents to circulate elsewhere, they may get into the power supply, the signal ground, etc, worse
yet, they may form a loop and radiate noise. Any of these cases results in degraded amplifier performance. The logical returns for the output
noise currents associated with Class-D switching are the respective PGND pins for each channel. The switch state diagram illustrates that
PGND is instrumental in nearly every switch state. This is the perfect point to which the output noise ground trace should return. Also note that
output noise ground is channel specific. A two channel amplifier has two seperate channels and consequently must have two seperate output
noise ground traces. The layout of the PAM8001 offers separate PGND connections for each channel and in some cases each side of the
bridge. Output noise grounds must be tied to system ground at the power in exclusively. Signal currents for the inputs, reference, etc need to be
returned to quite ground. This ground is only tied to the signal components and the GND pin, and GND then tied to system ground.
PCB Layout Example
Figure 2 Top Layer