AMD Am79C930 - Manual (Page 136)

AMD P R E L I M I N A R Y
136 Am79C930
ISA ACCESS
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
t
i
1 LA[23:17] valid setup to BALE
↓
60 ns
t
i
2 BALE
↑
to BALE
↓
pulse width 25 ns
t
i
3 LA[23:17] valid hold from BALE
↓
12 ns
t
i
4 LA[23:17] valid setup to CMD ↓ Note 1 80 ns
t
i
7 SA[16:0] valid setup to CMD ↓
Note 1 25 ns
t
i
8 CMD ↓
to CMD ↑
pulse width Note 4 6*T
CLKIN
ns
t
i
9 SA[16:0] valid setup to BALE
↓
20 ns
t
i
10 Data valid delay from RCMD ↓
Notes 2, 5, 6 53 X T
CLKIN
ns
t
i
11 Data valid setup to WCMD ↓ Note 3 –75 ns
t
i
12 SA[16:0] valid hold from CMD ↑ Note 1 20 ns
t
i
13 CMD ↑
to CMD ↓
pulse width Note 1 55 ns
t
i
14 Data valid hold from RCMD ↑
Note 2 0 ns
t
i
15 Data valid hold from WCMD ↑
Note 3 20 ns
t
i
16 Data disabled from RCMD ↑ Note 2, 6 20 ns
t
i
20 IOCHRDY ↓ delay from CMD ↓ Notes 1, 7 60 ns
t
i
21 IOCHRDY
↓
to IOCHRDY
↑
Notes 5, 6, 7 0 130 + ns
pulse width 53 X T
CLKIN
t
i
22 CMD ↑
delay from IOCHRDY
↑
Notes 1, 7 35 ns
t
i
23 BALE ↑ delay from CMD ↑ Note 1 20 ns
t
i
25 Data valid delay from IOCHRDY ↑ Note 7 –T
CLKIN
25 ns
t
i
26 LA[23:17] valid hold from CMD ↓
Note 1 –15 ns
t
i
30 AEN valid setup to CMD ↓
Note 1 80 ns
t
i
31 AEN valid hold from CMD ↑
Note 1 15 ns
t
i
32 AEN valid setup to BALE
↓
60 ns
t
i
34 Data enabled from RCMD ↓ Notes 2, 4 0 110 ns
Notes:
1. CMD = one of: MEMR , MEMW , IOR or IOW .
2. RCMD = one of: MEMR , or IOR .
3. WCMD = one of: MEMW , or IOW .
4. If no wait states are incurred.
5. The max value for this parameter assumes the following worst case situation:
Value Worst Case
0 FLASH and SRAM wait states set at “3.”
1 Host performs ISA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2 ISA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3 Host performs ISA READ cycle immediately following completion of ISA WRITE cycle.
4 After completion of first embedded 80188 access to FLASH, posted ISA WRITE executes to SRAM;
ISA READ stycle is being held in wait state.
5 After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
6 After completion of second embedded 80188 access to FLASH, ISA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
7 At SRAM READ cycle completion, data is delivered to ISA bus and wait state is exited.
6. Parameter is not included in production test.
7. Parameter only applies when IOCHRDY is deasserted.