Technical description, Features, I/o registers definition - control and status – Impulse 5103 User Manual
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Technical Description
Sealevel Systems ACB-MP.PCI Page
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Technical Description
The ACB-232.LPCI utilizes the Zilog 85230 Enhanced Serial Communications Controller (ESCC). This chip
features programmable baud rate, data format and interrupt control. Refer to the ESCC Users Manual for details on
programming the 85230 ESCC chip.
Features
• One channel of synchronous or asynchronous communications using the Zilog Z85230 chip
• EIA/TIA-232 Signals supported TD, RD, CTS, RTS, DCD, DSR, DTR, TXC, RXC, TSET, RI
• Programmable options for Transmit clock as input or output
• Software programmable baud rate
Internal Baud Rate Generator
The baud rate of the ESCC is programmed under software control. The standard oscillator supplied with the board is
7.3728 MHz. However, other oscillator values can be substituted to achieve different baud rates.
I/O Registers Definition - Control and Status
The control and status registers occupy 16 consecutive locations. The following tables provide a functional
description of the bit positions.
X = do not care
{ }= always this value
Address Mode
D7 D6
D5
D4
D3
D2
D1
D0
Base+4
RD {0} IRQST
{0}
{0}
{0}
{0}
{0}
{0}
Base+4
WR X X
X
X
X
X
X
X
Base+5
RD {0}
{0}
SYNCA_RTS SYNCA_CTS {0}
{0}
{0}
{0}
Base+5
WR X X
SYNCA_RTS
SYNCA_CTS
X
X
X
X
Base+6
RD {0}
{0}
{0}
TXOUT
RIOUT
DSROUT
TSETSLA RXCOPTA
Base+6
WR X
X
X
TXOUT
RIOUT
DSROUT
TSETSLA RXCOPTA
Base+14
RD SD7 SD6 SD5
SD4
SD3 SD2
SD1
SD0
Base+15
RD SD15
SD14 SD13
SD12
SD11 SD10 SD9
SD8
Field Description
Base +4
IRQST
SCC interrupt status: 1 = No interrupt pending on IUSC; 0 = Interrupt pending on IUSC.
Base +5
SYNCA_RTS
SYNCA _RTS – 0 = SYNCA is high, 1 = SYNCA connected to RTS ( 0 on power up )
SYNCA_CTS
SYNCA_CTS – 0 = SYNCA is high, 1 = SYNCA connected to CTS ( 0 on power up )
Base +6
TSETSLA
CHAN A – TSET clock source 0 = TRXCA as source,
1= received TXC as source ( 0 on power up )
RXCOPTA
RXCOPTA – 0 = selects received RXC for RTXCA,
1 = selects SCC PCLK for RTXCA ( 0 on power up )
DSROUT
DSROUT – 0 = DSR not routed to SCC
1 = DSR routed to SCC DCDB (0 on power up)*
RIOUT
RIOUT – 0 = RI not routed to SCC
1 = RI routed to SCC CTSB (0 on power up)**
TXOUT
TXOUT – 0 = TXD routed from SCC to 1488
1 = Forces TXD always a high (for idle mark bug in ESCC)***
Base +14 and 15
SD0-SD15
Optional security feature. Unique value per customer or application. ( default value = FFFF)
* DSR- is connected to Port B DCD on the 85230 only when this bit is set to a 1. If 9015 compatibility is
required, this bit must be set as part of the SCC initialization.
** RI- is connected to Port B CTS on the 85230 only when this bit is set to a 1. If 9015 compatibility is required,
this bit must be set as part of the SCC initialization.