Teledyne LeCroy TA700 Compliance User Guide - Manual (Page 22)

• 1.01
PCI DEVICE SPEED (AS INDICATED BY DEVSEL#) TEST
There are four sets of transactions that must be executed in this test. The first set is a memory read
command followed by a memory write command both with one data phase, this set is repeated four
times. Then the second set is an I/O read followed by an I/O write command both with one data phase,
this set is repeated two times on active motherboards (like computer systems) or four times on passive
boards because. Please note on active boards the tests for subtractive and below subtractive I/O target
speed can not be executed since the processor or the bridge may respond. The third set is a
configuration read followed by a configuration write command both with one data phase. This set is
repeated four times. The last section is a special cycle command which is not repeated.
Medium Speed Memory
Slow Speed Memory
Compliance Test
22 Rev. 1.0