Teledyne LeCroy TA700 Compliance User Guide - Manual (Page 41)

• 1.05
PCI BUS MULTI-DATA PHASE TARGET ABORT CYCLES
There are five sets of transactions that must be executed in this test. The first set is a memory read
command followed by a memory write command both with two data phases and the data of write
command is 00000000H. This set is repeated three times. The second set is a configuration read
followed by a configuration write command both with two data phases and the data of write
command is 00000000H. This set is repeated three times. The third section is a memory read
multiple command with three data phases that is repeated three times. The fourth section is a
memory read line command with three data phases that is repeated three times. The last section is a
memory write & invalidate command with three data phases (data value equal to 00000000H) that
is repeated three times.
Compliance Test
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