Teledyne LeCroy QPHY-DDR2 - Manual (Page 43)

QPHY-DDR2 Software Option
QPHY-DDR2-OM-E Rev A
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Write Bursts
tDQSS, DQS latching rising transitions to associated CK edge
CK rising edge at VREF level to DQS rising edge at VREF level, see Figure 26.
Figure 26. Burst write operation [JESD79-2E figure 39]
tDQSH, DQS Input High Pulse Width
DQS High pulse width at VREF level, see Figure 27.
Figure 27. Data input (write) timing [JESD79-2E figure 38]
tDQSL, DQS Input Low Pulse Width
DQS Low pulse width at VREF level, see Figure 27.
tDSS, DQS Falling Edge to CK Setup Time
Time from DQS falling edge at VREF level to CK rising edge at VREF level, see Figure 27.
tDSH, DQS Falling Edge Hold Time from CK
Time from CK rising edge at VREF level to DQS falling edge at VREF level, see Figure 27.