Teledyne LeCroy QPHY-DDR2 - Manual (Page 7)

QPHY-DDR2 Software Option
QPHY-DDR2-OM-E Rev A
7
INTRODUCTION TO QPHY-DDR2
QPHY-DDR2 is an automated test package performing all of the real time oscilloscope tests for Double Data Rate
in accordance with JEDEC Standard No. 79-2E. The software can be run on the LeCroy SDA/DDA/WavePro
740Zi and 760Zi and all SDA/DDA/WaveMaster 8Zi oscilloscopes.
Required equipment

SDA/DDA/WavePro 740/760Zi or SDA/DDA/WaveMaster 8Zi oscilloscope

Four D620 Probes with WL-Plink Prolink probe body

Alternatively, D610 probes may be used if the voltage swing of the signal is within +/- 2.5Vp-p.

TF-DSQ Probe Deskew and Calibration Fixture (not needed if using a Zi oscilloscope)
SIGNALS MEASURED
The compliance test requires probing the following signals (# is the negative polarity of the differential signal):
CK, CK# Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing
of the positive edge of CK and negative edge of CK#. Output (read) data is referenced to the crossings of CK and
CK# (both directions of crossing).
DQ Input/Output
Data Input/Output: Bi-directional data bus.
DQS, DQS# Input/Output
Data Strobe: output with read data, input with write data. This signal is in phase with read data and 90 degrees
out of phase with write data. The data strobes DQS may be used in single ended mode or paired with optional
complementary signal DQS# to provide differential pair signaling to the system during both reads and writes.
ADD/CTRL
In addition to the Clock, Data and Strobe signals, address and control signals can also be measured. Bank
Address (BA0
– BA2), Chip Select (CS), Command Inputs (RAS, CAS and WE), Clock Enable (CKE) and On Die
Termination (ODT) can all be specified as the signal under test.
BASIC FUNCTIONALITY
The functionality is extracted from JEDEC Standard No. 79-2E section 3.
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and
continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an
Active command, which is then followed by a Read or Write command.
Prior to normal operation, the DDR2 SDRAM must be initialized.