Teledyne LeCroy QPHY-LPDDR2 - Manual (Page 4)

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QPHY-LPDDR2-OM-G Rev B
D2) Demo of Eye Diagram (Debug) ......................................................................................................................... 34
D3) Demo of All tests ............................................................................................................................................... 34
D4) Demo of All CKdiff-DQSdiff-DQse tests ............................................................................................................ 34
QPHY-LPDDR2 VARIABLES .................................................................................................. 35
General Variables ..................................................................................................................................................... 35
DUT Speed Grade in MT/s ............................................................................................................................... 35
DQ Signal Name ............................................................................................................................................... 35
DQS Signal Name............................................................................................................................................. 35
Clock Signal Name ........................................................................................................................................... 35
DUT Power Supply VDDQ ................................................................................................................................ 35
Script Settings .......................................................................................................................................................... 35
Save Acquired Waveforms ............................................................................................................................... 35
Silent mode control ........................................................................................................................................... 35
Stop On Test to review results .......................................................................................................................... 35
Waveform Path ................................................................................................................................................. 35
Demo Settings .......................................................................................................................................................... 35
Use Stored Waveforms ..................................................................................................................................... 35
Recalled Waveform File Index (5 digits) ........................................................................................................... 35
Define format used to set trace names ............................................................................................................. 36
Use Stored Trace for Speed Grade .................................................................................................................. 36
Advanced Settings ................................................................................................................................................... 36
Clock Period per Screen Division ..................................................................................................................... 36
Number of cycles for Clock test ........................................................................................................................ 36
Max. Number Of Samples Per Clock Period .................................................................................................... 36
Configuration Specific Variables............................................................................................................................... 36
XX Channel Gain .............................................................................................................................................. 36
XX Channel Index ............................................................................................................................................. 36
XX Channel Invert ............................................................................................................................................. 36
XX Channel Offset ............................................................................................................................................ 36
Select Signal Under Test if many ..................................................................................................................... 37
QPHY-LPDDR2 LIMIT SETS ................................................................................................... 38
LPDDR2-466 ............................................................................................................................................................ 38
LPDDR2-533 ............................................................................................................................................................ 38
LPDDR2-667 ............................................................................................................................................................ 38
LPDDR2-800 ............................................................................................................................................................ 38
LPDDR2-933 ............................................................................................................................................................ 38
LPDDR2-1066 .......................................................................................................................................................... 38
QPHY-LPDDR2 TESTS ........................................................................................................... 38
Clock Tests ............................................................................................................................................................... 38
tCK(avg), Average Clock Period ................................................................................................................................ 38
tCK(abs), Absolute Clock Period ................................................................................................................................ 38
tCH(avg), Average High Pulse Width ......................................................................................................................... 39
tCL(avg), Average Low Pulse Width .......................................................................................................................... 39
tCH(abs), Absolute High Pulse Width ........................................................................................................................ 39
tCL(abs), Absolute Low Pulse Width .......................................................................................................................... 39
tJIT(duty), Half Period Jitter ....................................................................................................................................... 40
tJIT(per), Clock Period Jitter ...................................................................................................................................... 40
tJIT(cc), Cycle to Cycle Period Jitter .......................................................................................................................... 40
tERR(n per), Cumulative Error ................................................................................................................................... 40
Eye Diagram ............................................................................................................................................................ 41
Write Burst (Inputs) .................................................................................................................................................... 41
Read Burst (Outputs) ................................................................................................................................................. 41
Electrical Tests ......................................................................................................................................................... 41