Teledyne LeCroy QPHY-LPDDR2 - Manual (Page 7)

QPHY-LPDDR2 Software Option
QPHY-LPDDR2-OM-G Rev B
7
INTRODUCTION TO QPHY-LPDDR2
QPHY-LPDDR2 is an automated test package performing all of the real time oscilloscope tests for Double
Data Rate in accordance with JEDEC Standard No. 209-2B. The software can be run on the LeCroy
SDA/DDA/WavePro 740Zi and 760Zi, all SDA/DDA/WaveMaster 8Zi, and WaveRunner 625Zi and
WaveRunner 640Zi oscilloscopes.
Required equipment
• SDA/DDA/WavePro 740/760Zi or SDA/DDA/WaveMaster 8Zi or WaveRunner 640Zi/625Zi
oscilloscope
• Four D620 Probes with WL-Plink Prolink probe body
• Alternatively, D610 probes may be used if the voltage swing of the signal is within +/- 2.5Vp-p.
• TF-DSQ Probe Deskew and Calibration Fixture (not needed if using a Zi oscilloscope)
SIGNALS MEASURED
The compliance test requires probing the following signals (# is the negative polarity of the differential
signal):
CK, CK# Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge of CK#. Output (read) data is referenced to the
crossings of CK and CK# (both directions of crossing).
DQ Input/Output
Data Input/Output: Bi-directional data bus.
DQS, DQS# Input/Output
Data Strobe: output with read data, input with write data. This signal is in phase with read data and 90
degrees out of phase with write data.
ADD/CTRL
In addition to the Clock, Data and Strobe signals, address and control signals can also be measured.
Bank Address (BA0 – BA2), Chip Select (CS), Command Inputs (RAS, CAS and WE), Clock Enable
(CKE) and On Die Termination (ODT) can all be specified as the signal under test.
BASIC FUNCTIONALITY
The functionality is extracted from JEDEC Standard No. 209-2B.
Read and write accesses to the LPDDR2 SDRAM are burst oriented; accesses start at a selected location
and continue for a burst length of four or eight or sixteen in a programmed sequence. Accesses begin
with the registration of an Active command, which is then followed by a Read or Write command.
Prior to normal operation, the LPDDR2 SDRAM must be initialized.