MagTek TRIPLE TRACK Delta ASIC - Manual (Page 13)

Triple Track ASIC
9
Tdh (DATA Hold) = 0 ns minimum
Time from rising edge of STROBE that DATA is still valid.
TstbL_min (STROBE low minimum) = 500 ns minimum for CLEAR-STROBE (1
st
STROBE), 12.4 μs
minimum for STOP-STROBE, and 250 ns minimum otherwise. Allowable STROBE width (active-
low).
TstbH_min (STROBE high minimum) = 500 ns minimum for the time between the rising edge of
CLEAR-STROBE (1
st
STROBE) and the falling edge of STOP-STROBE; 250 ns minimum otherwise.
Allowable duration for STROBE to be high for recognition by the ASIC.
Trst (Reset) = 1
μs minimum (not shown in timing diagram)
VDD low-time to guarantee a reset for the ASIC.
DATA extraction rate = 1 / Twd to 1 / (TstbL_min+TstbH_min) = 4 bits/sec to 2 Mbits/sec
Maximum STROBE rate when it is not required that the DATA line be readable = 10MHz
Strobing at this limit is useful for reducing the time required to reset the chip. This limit is applicable
only after the completion of the two-STROBE handshake.
PREAMBLE KEY
Last bit shifted out Æ First bit shifted out
21006536/37 Revision ‘A/B/C’
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21006529/39 Revision ‘B’ 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21006540/41 Revision ‘A’ “Old” Mode 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21006540/41 Revision ‘A’ “New” Mode 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
‘1’ represents a low voltage level and ‘0’ represents a high voltage level.
The 21006540/41 is a “3V only” part. “Old” Mode for this chip is backwards compatible to
21006529/39. “New” Mode is not backwards compatible.
Note that 21006529/39 Revision ‘A’ was never released to production.