MagTek TRIPLE TRACK Delta ASIC - Manual (Page 9)

Triple Track ASIC
5
To identify which track is providing data, the controller must count the issued strobes. If fewer than three
tracks are implemented, the “empty” tracks, in addition to the required “handshake” and “preamble” must
still be extracted to reach the desired data.
The alternating data retrieval direction allows for the reading of cards swiped in either direction without
using micro-controller memory to store all the card data. For both directions of card swipe, the card data
can be verified for integrity before transmission to the host.
There are three ways to clear the on-chip memory of the ASIC. Clearing the buffer sets the data therein to
all ‘zeroes’ (high level). One way is to simply complete the “ABCCBAABCCBAABCCBAABCCBA”
data extraction sequence. Counting from first STROBE pulse issued upon first indication of the Buffer-
Ready state (be it the ZEROES FLAG or the AUXILIARY FLAG), there are a total of 2+16+8*3*608 =
14,610 STROBE pulses required to trigger the memory clear. DATA will go low, if not already the case,
in acknowledgement to the 14,610
th
rising edge of STROBE, the memory clear signal. After a period of
Tsc, DATA will return to its high idle state; however, this action may be delayed. If a card happens to be
in the process of being swiped at the time of the normal expiration of Tsc (see “Shift-Out Timing”), then
the ASIC will wait until this card is gone before re-arming and returning DATA to its high idle state.
In all future versions of this ASIC, DATA will return to a high state after each rising edge of STROBE,
including the 14,610
th
. There will be a delay of up to 8 ms before the reset completes and the ASIC is re-
armed, but there will no longer be an increase in this delay-to-re-arm due to a swipe-in-progress, nor will
there be an indication on DATA when the reset has completed.
Cycling power to the ASIC is the second way to clear the on-chip memory. The ASIC requires little
supply current, enabling it to be powered in many applications by a low-impedance micro-controller pin if
desired.
In this version of the ASIC, a watchdog timeout of 262 to 630 milliseconds will also clear the on-chip
memory of the ASIC if a STROBE pulse is not detected under certain conditions. The watchdog timer
begins to run from the initial falling edge of DATA following a card swipe, indicating the ZEROES
FLAG for ISO cards. The CLEAR STROBE must be issued prior to the expiration of the watchdog to
avoid data loss. In the case of ISO cards, the timeout that applies to the expectation of the second
STROBE of the required handshake, the STOP STROBE, begins at the second falling edge of DATA,
the AUXILIARY FLAG. The previous statement assumes that the ZEROES FLAG was cleared prior to
internal assertion of the AUXILIARY FLAG. The watchdog “looking” for a reset from the falling edge
of STOP-STROBE (2
nd
STROBE) actually begins at the latter of the falling edge of DATA indicating
the AUXILIARY FLAG or the falling edge of a valid CLEAR-STROBE (1
st
STROBE). This
complexity is required to keep compatibility with some non-ISO cards (see “SHIFT-OUT PROTOCOL –
CARDS ALLOWING 13 OR MORE CONSECUTIVE ZERO-BITS IN THE DATA FIELD”). With the
falling edge of the STOP-STROBE (2
nd
STROBE), the watchdog resumes operation with each falling
edge of STROBE clearing the watchdog timer. To maintain future compatibility, do not rely solely on
the watchdog timeout to clear the chip’s memory. Instead, use the other methods outlined in this
document for clearing memory.
After DATA initially falls to its Buffer-Ready state, the ASIC’s decoding circuits will ignore further card
signals until the memory is cleared. In this version of the ASIC, any swipe in progress when the memory