MagTek TRIPLE TRACK Delta ASIC - Manual (Page 7)

Triple Track ASIC
3
SHIFT-OUT PROTOCOL – ISO FORMAT CARDS AND MOST OTHERS
The magnetic-stripe card formats most commonly used, including the ISO format, do not allow 13
consecutive zero-bits to occur in the actual data field. This section of the specification applies to only
these commonly occurring cards. If your application requires the reading of custom-data-formats that do
allow 13 consecutive zero-bits to appear in the data-field (excluding the “leading” and “trailing” zero-
bits), then refer to the “SHIFT-OUT PROTOCOL – CARDS ALLOWING 13 OR MORE
CONSECUTIVE ZERO-BITS IN THE DATA FIELD” section located near the end of this specification.
DATA is the sole output of the ASIC and is normally held high. Once the ASIC has qualified a head
signal as a magnetic stripe card, it begins to store data from the card in its buffer. In general, after the
card is read, the DATA line transitions from high to a low level (ZEROES FLAG) indicating the Buffer-
Ready state. This falling edge of DATA is the signal to a micro-controller that the on-chip memory of the
ASIC contains data to be read. After a “handshake” sequence, the data is extracted (read from the buffer
memory) by pulsing the STROBE input low to advance the data pointer that steers the data to the DATA
pin. During data extraction and when the STROBE input is low, a low on DATA represents a “one” bit
and a high represents a “zero” bit. The state of DATA is indeterminate after each rising edge of the
controller-issued STROBE, until the next falling edge of STROBE.
STROBE is a digital input to the ASIC and should be normally held high. When the DATA line goes
low at the end of a card swipe, STROBE should be pulsed low twice to complete the required
“handshake” and shift out stored data in the ASIC buffer to the DATA output. The STROBE pin is a
Schmitt-trigger input.
The on-chip buffer (memory) is fixed at a size of 608 bits for each of the three magnetic stripe tracks,
1824 bits total. The storage of each track begins with the first “one-bit” obtained from the card. The
zero-bits that precede the first one-bit will not be stored. After detecting the first one-bit, the ASIC stores
up to 608 bits per track; any bits exceeding this amount will be lost. These lost bits are guaranteed to be
zero-bits for ISO-encoded cards.
Note that some damaged cards may have one or more initial zero-bits with media scratches that may
appear as one-bits to some types of readers. This ASIC is highly immune to misinterpreting even deeply
scratched zero-bits, and thus the full 608 bits will be available for real data, starting from the first encoded
one-bit encountered on the card. Also note that in the case of a backwards swipe, the ISO Longitudinal
Redundancy Check (LRC) may have trailing zero-bits that are not stored in the chip’s buffer. These
missing bits are easily reconstructed with proper firmware.
Extraction of the data, as initiated by STROBE, proceeds in the order it was received for track ‘A’, ‘B’,
and then ‘C’. When the data pointer reaches the last position of the 1824 bit/3-track memory, it cycles
back through the data in opposite order. To clarify, the data is shifted out first in the order it was received
for track ’A’ ‘B’ and then track ’C’. The ASIC does not determine “which end of the data is which”, but
simply reports the data as it was received. Next, the opposite direction data Shift-Out also occurs in the
order of track ‘C’, ‘B’, and then ‘A’, as if an audio tape were being “rewound”. This process of data
output in alternating order will occur for maximum of four (4) forward-and-back cycles (total path =
ABCCBAABCCBAABCCBAABCCBA) as long as the micro-controller provides pulses to the STROBE
pin that meet the timing requirements and the ASIC is not reset.