Campbell Scientific AM16/32A Multiplexer - Manual (Page 12)

AM16/32A Relay Analog Multiplexer
RES CLK GND 12V
O N
MUXPOWER
SHIELD
CR800,
CR850
CR10X,
CR3000,
CR1000
CR23X,
CR5000
21X CR7
G G
12 V 12 V 12 V +12 V 12 V
G G G
C1-C4 C1-C8 C1-C8 EXCIT 1-4 EXCITATION
C1-C4 C1-C8 C1-C8 C1-C8 725 Card
Control
FIGURE 3. AM16/32A to Datalogger Power/Control Hookup
With the 21X or CR7 the AM16/32A connects to the 12 VDC and “ ”
terminals for power. One control port is used for reset, and one switched
excitation channel is used for clock (on 725 card with CR7). If a switched
excitation port is not available, an additional control port can be used to
provide clock pulses to the multiplexer.
4.1.1 Reset
The reset (“RES”) line is used to activate the AM16/32A. A signal in the
range of +3.5 to +16 VDC applied to the reset terminal activates the
multiplexer. When this line drops lower than +0.9 VDC, the multiplexer
enters a quiescent, low-current-drain state. In the quiescent state the common
(“COM”) terminals are electrically disconnected from all of the sensor input
channels. Reset should always connect to a datalogger control port. Instruction
86 (option code 41 - 48 to activate, and 51 - 58 to deactivate) is generally used
to activate/deactivate the multiplexer, however, in the case of the 21X or CR7
with older PROMS, Instruction 20 is commonly used. The CR800, CR850,
CR3000, CR5000, and CR1000 uses the PortSet instruction to control the reset
line.
4.1.2 Clock
Pulsing the AM16/32A “CLK” line high (“RES” line already high) advances
the channel. When reset first goes high, the common terminals ODD H,
ODD L and EVEN H, EVEN L are disconnected from all sensor input
terminals. With the panel switch in “4x16” mode, when the first clock pulse
arrives the “COM” terminals are switched to connect with sensor input channel
1 (blue lettering) consisting of 1H, 1L, 2H, and 2L. When a second clock
pulse arrives the common lines are switched to connect to channel 2 (3H, 3L,
4H, 4L). The multiplexer advances on the leading edge of the positive going
clock pulse. The voltage level must fall below 1.5 VDC and then rise above
3.5 VDC to clock the multiplexer. The CLK pulse should be at least 1 ms
long. A delay (typically 10 to 20 ms) is inserted between the beginning of the
CLK pulse and the measurement instruction to ensure sufficient settling time
for relay contacts.
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