Advantech RISC SOM-A2558 - Manual (Page 30)

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User’s Manual for Advantech SOM-A2558 series module V1.00
30
A33 DATA16 IO SoC PXA255 system data 16 No pulling
B34 DATA17 IO SoC PXA255 system data 17 No pulling
A34 DATA18 IO SoC PXA255 system data 18 No pulling
B35 DATA19 IO SoC PXA255 system data 19 No pulling
A35 DATA20 IO SoC PXA255 system data 20 No pulling
B36 DATA21 IO SoC PXA255 system data 21 No pulling
A36 DATA22 IO SoC PXA255 system data 22 No pulling
B37 DATA23 IO SoC PXA255 system data 23 No pulling
A37
nBUF_SDCA
S
O
SDRAM CAS. Connect to the
column address strobe (CAS) pins
for all banks of SDRAM.
No pulling
B38
nBUF_SDCS
2
O
SDRAM CS for banks 2. Connect to
the chip select (CS) pins for SDRAM.
For the PXA255 processor nSDCS0
can be Hi-Z, Nsdcs1-3 cannot.
No pulling
A38 BUF_DQM1 O
SDRAM DQM for data bytes 1.
Connect to the data output mask
enables (DQM) for SDRAM.
No pulling
B39
BUF_SDCLK
2
O
SDRAM Clock 2. Connect
BUF_SDCLK[2] to the clock pins of
SDRAM in bank pairs 2/3. They are
driven by either the internal memory
controller clock, or the internal
memory controller clock divided by
2. At reset, all clock pins are free
running at the divide by 2 clock
speed and may be turned off via free
running control register bits in the
memory controller. The memory
controller also provides control
register bits for clock division and
deassertion of each SDCLK pin.
SDCLK[2:1] control register
assertion bits are always deasserted
upon reset.
No pulling
A39 nBUF_IOIS16 I
IO Select 16. Acknowledge from the
PCMCIA card that the current
address is a valid 16 bit wide I/O
address.
Pull high
with
100Kohm
B40 nBUF_PWE O
PCMCIA write enable. Performs
writes to PCMCIA memory and to
PCMCIA attribute space. Also used
as the write enable signal for
Variable Latency I/O.
No pulling
A40 KEYPAD_IRQ I
GPIO pin. Advantech default
function is used as matrix Keypad
IRQ. The pin directly connects to
PXA255 GPIO2 (L13 pin). If user
doesn’t use the matrix key pad
No pulling