Cirrus Logic CS160x - Manual (Page 7)

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3.3 Routing for ZCD and CS Pins for CS1501
The ZCD and the CS pins are the most sensitive pins on the IC. Since the sources of these signals are
close to the switching activity of the gate drive pin (GD), care must be taken to route these signals away
from noise sources. Since the ZCD pin is very close to the ground pin, which is the return current path of
the noisy gate switching currents, it is important to use a high-frequency decoupling capacitor to prevent
noise from being injected into the node. The currents of the CS pin signals can be high. As the signal
comes from the source of the power MOSFET, it can be considerably noisy.
The pros and cons of common decoupling practices are examined below. In all figures, pin 1 is at the top
left-hand corner of the image.
3.3.1 Option 1
The ground return hits the decoupling capacitor with 2 branches — one going to the GND pin and the
other going to the 33 pF capacitor. This is the least desirable since the high frequency ground current can
easily find a low impedance path through the 33 pF decoupling capacitor instead of the GND path itself.
This layout is not recommended.
Figure 7. Decoupling Option 1 — Not Recommended
3.3.2 Option 2
A larger ground plane fills the area between the ground pad, the VDD capacitor negative and the 33 pF
capacitor of the ZCD pin. This decoupling practice should work in most designs. In some rare cases where
the gate return current is large and the gate loop area is high, option 3 is preferred. If there is no space
for an extra decoupling capacitor as in option 3, the gate resistance can be increased to limit the
magnitude of high-frequency, noisy current flowing through the IC.
Figure 8. Decoupling Option 2 — Good Performance