Cirrus Logic CRD4202-2 - Manual (Page 14)

CRD4202-2
14 DS549RD1B1
R53
0
C68
.022 uF
C69
220 pF
R52
NO POP
Y2
14.318 MHz
3 1
2
4
R51
2.2K
DGND DGND
+3.3VD
DGND
XTAL
_ O
U T
XTAL
_ IN
ID
1 #
ID
0 #
1)
2)
3)
4)
For PLL operation:
PLL (Phase Locked Loop)
Populate R54 = 1K (Disable MB audio)
DO NOT populate: Y1, C14, C15, and R55
Apply external oscillator to XTAL_IN (pin 2)
(CRD4202-2 will use 14.318 MHz test oscillator ECS-8FA3)
Populate R51, R52, R53, C68, and C69 according to
the desired input clock rate:
Clock rate (MHz) R51 R52 R53 C68 C69
14.31818 2.2K NO POP 0 ohm 0.022uF 220pF
24.576 NO POP NO POP NO POP NO POP NO POP
27 2.2K 0 ohm NO POP 0.022uF 220pF
48 2.2K 0 ohm 0 ohm 0.022uF 220pF
Test Clock Only
Figure 8. Phase Locked Loop