Cirrus Logic CRD4202-2 - Manual (Page 5)

CRD4202-2
DS549RD1B1 5
the input clock frequency. Location Y2 in Figure 8
is populated with a 14.31818 MHz surface mount-
ed clock oscillator (test clock) to demonstrate the
CS4202 PLL operation.
2.9 Component Selection
Great attention was given to the particular compo-
nents used on the CRD4202-2 board with cost, per-
formance, and package selection as the most
important factors. Listed are some of the guidelines
used in the selection of components:
• No components smaller than 0805 SMT pack-
age.
• Only single package passive components. No
resistor packs. This reduces the risk of crosstalk
between analog audio signals.
• All components except connectors are in sur-
face mount packages.
2.10 EMI Components
Optional capacitors or inductors may be included
to help the board meet EMI compliance tests, such
as FCC Part 15. Choose these component values
according to individual requirements.
3. GROUNDING AND LAYOUT
The component layout and signal routing of the
CRD4202-2 provide a good model for developing
new CNR add-in card designs.
3.1 Partitioned Voltage and Ground
Planes
It is critical for good audio performance to separate
digital and analog sections to prevent digital noise
from affecting the performance of the analog cir-
cuits. The analog section of the CRD4202-2 is
physically isolated from the digital section with a
0.10 inch partition. Partitioning is defined as the
absence of copper on all PCB signal layers. The an-
alog and digital sections have their own separate
ground planes. All analog components, power trac-
es, and signal traces are routed over the analog
ground plane. Digital components, power traces,
and signal traces are not allowed to crossover into
the analog section.
The CS4202 audio codec is placed at the transition
point between the analog and digital ground planes.
The analog and digital ground planes must be tied
together externally for the CS4202 to maintain
proper voltage references. For best results, the two
ground planes are tied together with a single 0.050
inch trace under the CS4202 near its digital ground
pins.
Data converters are generally susceptible to noise
on the crystal pins. In order to reduce noise from
coupling onto these pins, the area around the
24.576 MHz crystal and its signal traces are filled
with copper on the top and bottom of the PCB and
attached to digital ground.
A separate chassis ground provides a noise-free
reference point for all of the EMI suppression com-
ponents. The chassis ground plane is connected to
the analog ground plane at the external jacks.
3.2 AC-Link
According to the AC '97 revision 2.2 specification,
the AC-Link signals can have a maximum capaci-
tance (including traces, connectors, and circuitry)
of 47.5 pF on BIT CLK and SDATA_IN (assuming
a single codec). If this capacitance is exceeded,
timing violations may occur and cause the system
to malfunction. In order to avoid adding excessive
capacitance, do not add any EMI capacitors to
ground on any of the AC-Link lines. In addition,
keep the trace length of the AC-Link as short as
possible. Keeping the AC-Link trace length under 8
inches is strongly recommend.
3.3 CS4202 Layout Notes
Refer to the CS4202 Data Sheet for analog and dig-
ital partitioning guidelines and bypass capacitor
placement. Pay special attention to the location of
bypass capacitors on REFFLT, AFLT1, AFLT2,
and the placement of the power supply capacitors.