Cirrus Logic CS4228A - Manual (Page 13)

CS4228A
13
3. FUNCTIONAL DESCRIPTION
3.1 Overview
The CS4228A is a 24-bit audio codec comprised of
2 analog-to-digital converters (ADC) and 6 digital-
to-analog converters (DAC), all implemented us-
ing single-bit delta-sigma techniques. Other func-
tions integrated with the codec include independent
digital volume controls for each DAC, digital DAC
de-emphasis filters, ADC high-pass filters, an on-
chip voltage reference, and a flexible serial audio
interface. All functions are configured through a
serial control port operable in SPI mode and in I
2
C
mode. Figure 6 shows the recommended connec-
tions for the CS4228A.
3.2 Analog Inputs
3.2.1 Line Level Inputs
AINR+, AINR-, AINL+, and AINL- are the line
level analog inputs (See Figure 6). These pins are
internally biased to a DC operating voltage of ap-
proximately 2.3 VDC. AC coupling the inputs pre-
serves this bias and minimizes signal distortion.
Figure 6 shows operation with a single-ended input
source. This source may be supplied to either the
positive or negative input as long as the unused in-
put is connected to ground through capacitors as
shown. When operated with single-ended inputs,
distortion will increase at input levels higher than
-1 dBFS. Figure 7 shows an example of a differen-
tial input circuit.
Muting of the stereo ADC is possible through the
ADC Control Byte.
The ADC output data is in 2’s complement binary
format. For inputs above positive full scale or be-
low negative full scale, the ADC will output
7FFFFFH or 800000H, respectively.
3.2.2 High Pass Filter
Digital high pass filters in the signal path after the
ADCs remove any DC offsts present on the analog
inputs. The high pass filter helps prevent audible
“clicks” when switching between audio sources
downstream from the ADCs. The high pass filter
response, given in “High Pass Filter Characteris-
tics”, scales linearly with sample rate. Thus, for
High Rate Mode, the -3 dB frequency at a 96 kHz
sample rate will be equal to 96/44.1 times that at a
sample rate of 44.1 kHz.
+
-
0.1 µF
10 µf
10 k
+
-
4.7 k
10 k
AIN -
10 µF
VA
+
AIN +
2.2 nf
150
150
10 k
10 k
~ 8.5 k
signal
+
Figure 7. Optional Line Input Buffer