Cirrus Logic CS4228A - Manual (Page 18)

CS4228A
18
3.7 Control Port Signals
Internal registers are accessed through the control
port. The control port may be operated asynchro-
nously with respect to audio sample rate. However,
to avoid potential interference problems, the con-
trol port pins should remain static if no register ac-
cess is required.
The control port has 2 operating modes: SPI mode
and I
2
C mode. In both modes the CS4228A oper-
ates as a slave device. Mode selection is deter-
mined by the state of the SDOUT pin when RST
transitions from low to high: high for SPI, low for
I
2
C mode. SDOUT is internally pulled high to VL.
A resistive load from SDOUT to GND of less than
47 k
Ω
will enable I
2
C mode after a hardware reset.
3.7.1 SPI Mode
In SPI mode, CS is the CS4228A chip select signal,
CCLK is the control port bit clock input, and CDIN
is the input data line. There is no data output line,
therefore all registers are write-only in SPI mode.
Data is clocked in on the rising edge of CCLK.
Figure 13 shows the operation of the control port in
SPI mode. The first 7 bits on CDIN, after CS goes
low, form the chip address (0010000). The eighth
bit is a read/write indicator (R/W), which should al-
ways be low to write. The next 8 bits set the Mem-
ory Address Pointer (MAP) which is the address of
the register that is to be written. The following
bytes contain the data which will be placed into the
registers designated by the MAP.
The CS4228A has a MAP auto increment capabili-
ty, enabled by the INCR bit in the MAP register. If
INCR is zero, then the MAP will stay constant for
successive writes. If INCR is 1, then the MAP will
increment after each byte is written, allowing block
reads, or writes, of successive registers.
3.7.2 I
2
C Mode
In I
2
C mode, SDA is a bidirectional data line. Data
is clocked into and out of the port by the SCL clock.
The signal timing is shown in Figure 15 and 16. A
Start condition is defined as a falling transition of
SDA while the clock is high. A Stop condition is a
rising transition while the clock is high. All other
transitions of SDA occur while the clock is low.
The first byte sent to the CS4228A after a Start con-
dition consists of a 7 bit chip address field and a
R/W bit (high for a read, low for a write). The AD0
pin determines the LSB of the chip address field.
The upper 6 bits of the address field must be 00100
and the seventh bit must match AD0. If the opera-
tion is to be a write, the second byte is the Memory
Address Ponter (MAP), which selects the register
to be written. The succeeding byte(s) are data. If
the operation is to be a read, the second byte is sent
from the chip to the controller and contains the con-
tents of the register pointed to by the current value
of the MAP.
CS
CCLK
12 13 14 15
CDIN
CHIP ADDRESS (WRITE) MAP BYTE
0 0 1 0 0 0 0 0
MSB
DATA DATA +n
R/W
6 5 4 3 2 1 0
8 9 10 11 4 5 6 7 0 1 2 3 16 17 18 19 20 21 22
INCR
23
(input)
(input)
(input)
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Figure 14. Control Port Timing, SPI Slave Mode Write