Cirrus Logic CS42416 - Manual (Page 29)

DS602F2 29
CS42416
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
LSB M SB
20 clks
64 clks 64 clks
LS B MSB LS B M SB LSB M SB LSB M SB LSB MSB MSB
DAC1 DAC3 DAC5 DAC2 DAC4 DAC6
20 clks 20 clks 20 clks 20 clks 20 clks
Left Channel Right Channel
20 clks
A DC1 A DC3 A DC5 A DC2 A DC4 A DC6
20 clks 20 clks 20 clks 20 clks 20 clks
ADC_SDOUT
DAC_SDIN1
Figure 14. One-Line Mode #1 Serial Audio Format
One Line Data Mode #1, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
20
128 Fs 128 Fs Single-Speed Mode
128 Fs 128Fs Double-Speed Mode
DAC_LRCK
ADC_LRCK
DAC_SCLK
ADC_SCLK
LSB MSB
24 clks
128 clks
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB MSB
DAC1 DAC3 DAC5 DAC2 DAC4 DAC6
24 clks 24 clks 24 clks 24 clks 24 clks
Left Channel Right Channel
24 clks
ADC1 ADC3 ADC5 ADC2 ADC4 ADC6
24 clks 24 clks 24 clks 24 clks 24 clks
ADC_SDOUT
128 clks
DAC_SDIN1
Figure 15. One-Line Mode #2 Serial Audio Format
One Line Data Mode #2, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
Master Slave
24 256 Fs not supported Single-Speed Mode