Fpga register description, 1 code revision id - address 01h, 2 mclk source control - address 02h – Cirrus Logic CDB4245 User Manual
Page 12: Table 1. mclk2 source, Table 2. mclk1 source, Table 1. mclk2 source table 2. mclk1 source, Cdb4245
CDB4245
12
DS656DB1
6. FPGA REGISTER DESCRIPTION
6.1
CODE REVISION ID - ADDRESS 01H
Function:
Identifies the revision of the FPGA code. This register is Read-Only.
6.2
MCLK SOURCE CONTROL - ADDRESS 02H
6.2.1
MCLK2 SOURCE (BITS 5:4)
Default = 10
Function:
These bits select the source of the CS4245 MCLK2 signal. Table 1 shows the available settings.
6.2.2
MCLK1 SOURCE (BITS 1:0)
Default = 00
Function:
This bit selects the source of the CS4245 MCLK1 signal. Table 2 shows the available settings.
7
6
5
4
3
2
1
0
Rev7
Rev6
Rev5
Rev4
Rev3
Rev2
Rev1
Rev0
7
6
5
4
3
2
1
0
Reserved
Reserved
MCLK2.1
MCLK2.0
Reserved
Reserved
MCLK1.1
MCLK1.0
Table 1. MCLK2 Source
MCLK2.1
MCLK2.0
MCLK2 Source
0
0
Oscillator 2
0
1
MCLK2 position on Header 2
1
0
CS8416 RMCK
1
1
MCLK1
Table 2. MCLK1 Source
MCLK1.1
MCLK1.0
MCLK1 Source
0
0
Oscillator 1
0
1
MCLK1 position on Header 1
1
0
Reserved
1
1
MCLK2