Cirrus Logic CDB4245 - Manual (Page 2)

CDB4245
2 DS656DB1
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................... 4
1.1 Power ................................................................................................................................. 4
1.2 Grounding and Power Supply Decoupling ......................................................................... 4
1.3 CS4245 Audio CODEC ...................................................................................................... 4
1.4 CS8406 Digital Audio Transmitter ...................................................................................... 4
1.5 CS8416 Digital Audio Receiver .......................................................................................... 4
1.6 FPGA ................................................................................................................................. 5
1.7 Canned Oscillators ............................................................................................................. 5
1.8 External Control Headers ................................................................................................... 5
1.9 Analog Inputs ..................................................................................................................... 5
1.10 Analog Outputs ................................................................................................................ 5
1.10.1 DAC Outputs ....................................................................................................... 5
1.10.2 Auxiliary Outputs ................................................................................................. 5
1.11 Serial Control Port ............................................................................................................ 5
1.12 USB Control Port ............................................................................................................. 6
2. SYSTEM CLOCKING ............................................................................................................... 6
2.1 Clock Domain 1 .................................................................................................................. 6
2.2 Clock Domain 2 .................................................................................................................. 6
3. SYSTEM DATA ROUTING ....................................................................................................... 6
3.1 CS4245 SDIN Source ........................................................................................................ 6
3.2 CS8406 SDIN Source ........................................................................................................ 6
4. PC SOFTWARE CONTROL ..................................................................................................... 7
4.1 CDB4245 Controls Tab ...................................................................................................... 7
4.2 S/PDIF I/O Controls Tab .................................................................................................... 8
4.3 Register Maps Tab ............................................................................................................. 9
4.4 Pre-Configured Script Files ................................................................................................ 9
4.4.1 Oscillator Clock - ADC Ch 1 to DAC & SPDIF Out ............................................... 9
4.4.2 SPDIF Recovered Clock - SPDIF to DAC & ADC to SPDIF ............................... 10
5. FPGA REGISTER QUICK REFERENCE ............................................................................... 11
6. FPGA REGISTER DESCRIPTION ......................................................................................... 12
7. CDB CONNECTORS, JUMPERS, AND SWITCHES ............................................................. 15
8. CDB BLOCK DIAGRAM ..................................................................................................... 17
9. CDB SCHEMATICS ............................................................................................................... 18
10. CDB LAYOUT ...................................................................................................................... 26
11. REVISION HISTORY ............................................................................................................ 29