Cirrus Logic CS4297A - Manual (Page 28)

CS4297A
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4.14 Extended Audio ID Register (Index 28h)
ID[1:0] Codec Configuration ID. When ID[1:0] = 00, the CS4297A is the primary audio codec. When
ID[1:0] = 01, 10, or 11, the CS4297A is a secondary audio codec. The state of the ID[1:0] bits
is determined at power-up from the ID[1:0]# pins.
AMAP Audio Slot Mapping. The AMAP bit indicates whether the optional AC ’97 2.1 compliant AC-link
slot to audio DAC mapping is supported. This bit is a shadow of the AMAP bit in the AC Mode
Control Register (Index 5Eh). The PCM playback and capture slots are mapped according to
Table 7 on page 29.
VRA Variable Rate PCM Audio. The VRA bit indicates whether variable rate PCM audio is supported.
This bit always returns ‘0’, indicating that variable rate PCM audio is not available.
Default x200h. Where x is determined by the state of ID[1:0]# input pins. The Extended Audio ID Reg-
ister (Index 28h) is a read only register.
4.15 PCM Front DAC Rate Register (Index 2Ch)
SR[15:0] Front DAC Sample Rate. The SR[15:0] bits are read-only bits, and always read BB80h indicat-
ing 48 kHz sample rate.
Default BB80h. This value corresponds to 48 kHz sample rate.
4.16 PCM L/R ADC Rate Register (Index 32h)
SR[15:0] Left/Right ADC Sample Rate. The SR[15:0] bits are read-only bits, and always read BB80h in-
dicating 48 kHz sample rate.
Default BB80h. This value corresponds to 48 kHz sample rate.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ID1 ID0 0 0 0 0 AMAP 0 0 0 0 0 0 0 0 VRA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
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CS4297A