Figure 1. power up timing, Figure 3. clocks, Cs4297a – Cirrus Logic CS4297A User Manual
Page 8
Advertising
CS4297A
8
BIT_CLK
T
rst_low
T
rst2clk
T
vdd2rst#
Vdd
RESET#
Figure 1. Power Up Timing
Figure 2. Codec Ready from Startup or Fault Condition
BIT_CLK
T
sync2crd
CODEC_READY
SYNC
Figure 3. Clocks
BIT_CLK
SYNC
T
irise
T
ifall
T
orise
T
ifall
T
clk_high
T
clk_low
T
sync_high
T
sync_low
T
sync_period
T
clk_period
8
DS318PP6
CS4297A
Advertising