Cirrus Logic CS4352 - Manual (Page 12)

12 DS684F2
CS4352
4.3 Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats, as illustrated in Table 5 .
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship
between the LRCK, SCLK and SDIN, see
Figures 3 - 5 . For all formats, SDIN is valid on the rising edge of
SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2 and 48 cycles per LRCK period
in format 3.
For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-
nel Serial Audio Interface: A Tutorial, available at
www.cirrus.com .
Table 5. Digital Interface Format
Figure 3. I²S, up to 24-Bit Data
Figure 4. Right-Justified Data
Figure 5. Left-Justified up to 24-Bit Data
DIF1 DIF0 DESCRIPTION FORMAT FIGURE
0 0 I²S, up to 24-bit Data 0 3
0 1 Right-Justified, 24-bit Data 1 4
1 0 Left-Justified, up to 24-bit Data 2 5
1 1 Right-Justified, 16-bit Data 3 4
L R C K
S C L K
L e ft C h a n n e l R ig h t C h a n n e l
S D IN + 3 + 2 + 1 +5 +4 M S B -1 -2 -3 -4 -5 +3 +2 +1 + 5 + 4 -1 -2 -3 -4 M S B LS B LS B
L R C K
S C L K
L e ft C h a n n e l
S D IN -6 -5 -4 -3 -2 -1 -7 +1 +2 +3 +4 +5 M S B
R ig h t C h a n n e l
LS B M S B +1 +2 +3 +4 +5 LS B -6 -5 -4 -3 -2 -1 -7 M S B
L R C K
S C L K
L e ft C h a n n e l R ig h t C h a n n e l
S D IN +3 +2 +1 +5 +4 M S B -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 LSB M SB LS B