Cirrus Logic CS4352 - Manual (Page 15)

DS684F2 15
CS4352
4.9 Initialization and Power-Down Sequence Diagram
USER: Apply Power
Wait State
USER: Apply MCLK, SCLK, and LRCK
MCLK/LRCK Ratio Detection
USER: Remove
LRCK or MCLK
USER: change
MCLK/LRCK ratio
Analog Output
is Generated
USER: Apply RST
USER: Apply MCLK, SCLK, LRCK,
and release RST
Power-Down State
VQ and outputs low
VQ and outputs
ramp down
VQ and outputs ramp up