Cirrus Logic CS4360 - Manual (Page 23)

CS4360
DS517F2 23
4.3.2 Control Port Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section
6.1.2). For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 15-17.
4.4 De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 18 shows the de-emphasis curve for F
s
equal to
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in
sample rate, Fs.
Notes: De-emphasis is only available in Single-speed Mode.
L R C K
S C L K
L e ft C ha n n el R ig ht C h a n n el
S D IN + 3 + 2 + 1 + 5 + 4 M S B -1 - 2 -3 -4 -5 + 3 + 2 + 1 + 5 + 4 -1 -2 -3 -4 L S B M S B LS B
Figure 15. Left Justified up to 24-Bit Data
L R C K
S C L K
L e ft C ha n n el R ig ht C h a n n el
S D IN + 3 + 2 + 1 + 5 + 4 M S B -1 - 2 -3 -4 -5 + 3 + 2 + 1 + 5 + 4 -1 -2 - 3 -4 M S B L S B L S B
Figure 16. I 2 S, up to 24-Bit Data
L RC K
S C LK
L e ft C ha n ne l
S DIN + 6 + 5 + 4 + 3 + 2 + 1 + 7 -1 -2 -3 -4 -5 LS B
R ig h t C ha nn e l
M S B LS B + 6 + 5 + 4 + 3 + 2 + 1 + 7 -1 -2 -3 -4 -5 M S B L S B
Figure 17. Right Justified Data
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 18. De-emphasis Curve