Dsd - switching characteristics, Cs4382 dsd - switching characteristics – Cirrus Logic CS4382 User Manual
Page 10
10
DS514F2
CS4382
DSD - SWITCHING CHARACTERISTICS
(For KQZ T
A
= -10°C to +70°C; Logic 0 = GND; VLS = 1.8 V to 5.5 V; Logic 1 = VLS Volts; C
L
= 30 pF)
Note:
18. Min is 4 times 64x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The
proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins
Parameter
Symbol Min Typ
Max
Unit
Master Clock Frequency
4.096
-
38.4
MHz
MCLK Duty Cycle
(All DSD
modes)
40
50
60
%
DSD_SCLK Pulse Width Low
t
sclkl
20
-
-
ns
DSD_SCLK Pulse Width High
t
sclkh
20
-
-
ns
DSD_SCLK Frequency
(64x Oversam-
pled)
(128x Oversampled)
1.024
2.048
-
-
3.2
6.4
MHz
MHz
DSD_L / _R valid to DSD_SCLK rising setup time
t
sdlrs
20
-
-
ns
DSD_SCLK rising to DSD_L or DSD_R hold time
t
sdh
20
-
-
ns
sclkh
t
sclkl
t
DSD_L, DSD_R
DSD_SCLK
sdlrs
t
sdh
t
Figure 2. Direct Stream Digital - Serial Audio Input Timing