Figure 37. format 4 - right justified 20-bit data, Figure 38. format 5 - right justified 18-bit data, Figure 39. de-emphasis curve – Cirrus Logic CS4382 User Manual
Page 38: Figure 39, Cs4382
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38
DS514F2
CS4382
LRCK
SCLK
Left Channel
Right Channel
SDINx
6 5 4 3 2 1 0
9 8 7
15 14 13 12 11 10
1 0
6 5 4 3 2 1 0
9 8 7
15 14 13 12 11 10
17 16
17 16
32 clocks
19 18
19 18
Figure 37. Format 4 - Right Justified 20-bit Data
LRCK
SCLK
Left Channel
Right Channel
SDINx
6 5 4 3 2 1 0
9 8 7
15 14 13 12 11 10
1 0
6 5 4 3 2 1 0
9 8 7
15 14 13 12 11 10
17 16
17 16
32 clocks
Figure 38. Format 5 - Right Justified 18-bit Data
Figure 39. De-Emphasis Curve
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1
F2
3.183 kHz
10.61 kHz
SDINx
Channel
Pair x
Control
DAC
DAC
AOUTAx+
AOUTAx-
AOUTBx+
AOUTBx-
L
R
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, 3, or 4)
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