Cirrus Logic CDB5364 - Manual (Page 11)

DS625DB1 11
CDB5364
4.5 Power Supply Circuitry
Power is applied to the evaluation board through five binding posts (+5 V, +12 V, -12 V, VA and GND). The
GND connection is the common reference for power supplies. The +5 V binding post supplies digital power
for all logic devices. The +12 V and -12 V binding posts supply power for the Operational Amplifier input
buffers. The VA binding posts supplies power to the Analog Reference.
4.6 Grounding and Power Supply Treatment
As a high-peformance mixed-signal device, the CS5364 requires careful attention to power and grounding
arrangements to optimize CS5364 performance. The CDB5364 Evaluation Board provides an excellent ref-
erence example of an optimum two-layer board layout that places decoupling capacitors as close to the
CS5364 as possible and provides ground plane fill on both top and bottom layers.
4.7 FPGA Hardware
The on-board FPGA is utilized for several purposes. In addition to providing a method for configuring the
CS5364 in Software mode, it contains its own configuration registers that provide clock and data routing for
Master and Slave modes of the CS5364. The FPGA contains a multiplexer that selects which SDOUT line
is routed to the CS8406. It also contains a TDM2PCM engine that extracts channel pairs from a TDM stream
and sends them to the CS8406.
4.8 CS8406 S/PDIF Audio Transmitter
The system generates standard S/PDIF data using a CS8406 192 kHz Digital Audio Transmitter. The
CS8406 receives input data from the FPGA in PCM format and transmits S/PDIF data on both optical and
coaxial output connectors. The optical output connector is limited to a maximum speed of 96 kHz. The co-
axial connector supports Quad Speed 192 kHz clocking rates.
4.9 Serial Audio Interface
In addition to the standard S/PDIF outputs, the Customer Evaluation Board has been designed to allow
Master and Slave operation using the Serial Audio Interface (SAI) via the 14-pin header, J4, which includes
the signals MCLK, SCLK, LRCK, and the four serial data lines.
When the CS5364 is in Slave mode, SCLK and LRCK/FS must be supplied externally through the J4 head-
er.
4.10 Analog Input Buffer
The CDB5364 includes an example of an active low-noise, single-ended-to-differential analog input buffer
shown in the schematic drawings,
Figures 10 and 11 . Alternate active or passive, single-ended or differen-
tial topologies may be used as cost dictates. However, the high performance of the CS5364 may be com-
promised. Optimum device performance is met by buffering the CS5364 with a low noise structure that is
stable with a 2700 pF output load.