Cirrus Logic CS5372 - Manual (Page 12)

CS5371 CS5372
12 DS255F3
over which voltage reference noise affects the
CS5371/72 modulator dynamic range.
6.1. Voltage Reference Configurations
For a 2.5 V reference, the Linear Technology
LT1019-2.5 voltage reference yields low enough
noise if the output is filtered with a low pass RC fil-
ter as shown in Figure 6. The filtered version in
Figure 6 is acceptable for most spectral measure-
ment applications, but a buffered version with low-
er source impedance may be preferred for DC
measurement applications.
6.2. VREF Input Impedance
The switched-capacitor input architecture of the
VREF+ pin causes the input current required from
the voltage reference to change any time MCLK is
changed. The input impedance of the voltage ref-
erence input is calculated similar to the analog sig-
nal input impedance as [1 / (f * C)] where f is the
modulator clock frequency, MCLK, and C is the in-
ternal sampling capacitor. A 2.048 MHz MCLK
yields a voltage reference input impedance of ap-
proximately [1 / (2.048 MHz)*(20 pF)], or about
24 k
Ω.
6.3. Gain Accuracy
Gain accuracy of the CS5371/72 modulators is af-
fected by variations of the voltage reference input.
A change in the voltage reference input impedance
due to a change in MCLK could affect gain accura-
cy when using the higher source impedance con-
figuration of Figure 6. The VREF+ pin input
impedance and the external low-pass filter resistor
create a voltage divider for the output reference
voltage, reducing the effective voltage reference
input. If gain error is to be minimized, especially
when MCLK is to be changed, the voltage refer-
ence should have a low output impedance to mini-
mize the effect of the resistive voltage divider. A
buffered voltage reference configuration offers
lower output impedance and more stable gain
characteristics.
6.4. Gain Drift
Gain drift of the CS5371/72 modulators due to tem-
perature is around 5 ppm/°C, and does not include
the temperature drift characteristics of the external
voltage reference. Gain drift is not affected by the
modulator sample rate or by power supply varia-
tions.
7. DIGITAL FILTER INTERFACE
The CS5371/72 modulators are designed to oper-
ate with the CS5376A and CS5378 digital filters.
The digital filter generates the modulator clock and
synchronization signal inputs (MCLK and
MSYNC), while receiving the modulator data and
over-range flag outputs (MDATA and MFLAG).
The modulators produce an oversampled
∆Σ serial
10 Ω
To VREF+
To VREF -
0.1 µF 100 µF
+
+VA
2.5 REF
0.1 µF 10 µF
-VA
0.1 µF 10 µF
Figure 6. 2.5 Voltage Reference