Cirrus Logic CS5372 - Manual (Page 13)

CS5371 CS5372
DS255F3 13
bit stream at 512 kbits per second when operated
from a 2.048 MHz modulator clock.
7.1. Modulator Clock - MCLK
For proper operation, the CS5371/72 modulators
must be provided with a CMOS compatible clock
on the MCLK pin. MCLK is internally divided by
four to generate the modulator sampling clock.
MCLK must have less than 300 ps of in-band jitter
to maintain full performance specifications.
When used with the CS5376A or CS5378 digital fil-
ter, MCLK is automatically generated and is typi-
cally 2.048 MHz or 1.024 MHz. MCLK can be
generated by other means, using a crystal oscilla-
tor for example, and can run any rate between
100 kHz and 2.2 MHz. If MCLK is disabled, the
modulators are automatically placed into a micro-
power state. They are equipped with loss of clock
detection circuitry to force power down if MCLK is
removed.
The choice of MCLK frequency affects the perfor-
mance of the CS5371/72 modulators. They exhibit
the best dynamic range (SNR) performance with
faster MCLK rates because of increased oversam-
pling of the analog input signal. The modulators
exhibit the best total harmonic distortion (THD)
performance with slower MCLK rates because
slower sampling allows more time to settle the an-
alog input signal.
7.2. Modulator Data - MDATA
The CS5371/72 modulators output a
∆Σ serial bit-
stream to the MDATA pin, with a one’s density pro-
portional to the amplitude of the analog input signal
and a bit rate determined by the modulator sam-
pling clock. The modulator sampling clock is a di-
vide by four of MCLK, so for a 2.048 MHz MCLK
the modulator sampling clock and MDATA output
bit rate will be 512 kHz.
The MDATA output has a one’s density defined as
nominal 50% for no signal input, 86% for positive
full scale, and 14% for negative full scale. It has a
maximum positive over-range capability to 93%
and a maximum negative over-range capability to
7%. The one’s density of the MDATA output is de-
fined as the ratio of ‘1’ bits to total bits in the serial
bitstream output, i.e. an 86% one’s density has, on
average, a ‘1’ value in 86 of every 100 output data
bits.
When operated with the CS5376A or CS5378 dig-
ital filter, the full-scale 24-bit output codes range
from 0x5D1C41 to 0xA2EAAE with the internal
OFST disabled.
Note that for a full-scale input signal, 5 V
pp
with
VREF=2.5 V, the CS5371/72 and CS5376A/78
chipset does not output a maximum 24-bit 2’s com-
plement digital code of 0x7FFFFF, but instead a
lower scaled value to allow over-range capability.
7.3. Modulator Sync - MSYNC
To synchronize the analog sampling instant and
timing of the digital output bitstream, the
CS5371/72 modulators use an MSYNC signal.
When using the CS5376A or CS5378 digital filter,
MSYNC is automatically generated from a SYNC
signal input from the external system.
The MSYNC input is rising edge triggered and re-
sets the internal MCLK counter-divider so the ana-
log sampling instant occurs during a consistent
MCLK phase. It also sets the MDATA output tim-
ing so the bitstream can be properly sampled by
the digital filter input.
7.4. Modulator Flag - MFLAG
The CS5371/72 modulators are 4th order
∆Σ and
are therefore conditionally stable. The modulators
may go into an oscillatory condition if the analog in-
puts are over-ranged more than 5% past either
positive or negative fullscale.
If an unstable condition is detected, the modulators
collapse to a 1st order system until loop stability is
Table 1. Output coding for the CS5371/72 and digital
filter combination
Modulator Input
Signal
Digital Filter
Output Code
OFST=0 OFST=1
> + (VREF + 5%) Error Flag Possible
+VREF 5D1C41 5B3A71
0V 000000 FE21D8
-VREF A2EAAE A108DE
> - (VREF + 5%) Error Flag Possible