2 cs53l21 h/w control, Table 2. cs53l21 h/w mode control, Cdb53l21 – Cirrus Logic CDB53L21 User Manual
Page 16
16
DS700DB1
CDB53L21
3.2
CS53L21 H/W Control
The stand-alone “CS53L21 H/W Control” switch S5 controls the Hardware Mode options of the CS53L21.
A description of each switch is outlined in the following table. See the CS53L21 Data Sheet, Section 4.2
“Hardware M
ode” for further details on setting these switches.
Notes:
1. The
M/S
setting affects the CS53L21 only and is independent of S[1] setting
in the “FPGA H/W
Control”
switch S3.
These settings must be made manually by the user and have to be consistent.
2. The
I2S/LJ
setting affects the CS53L21 only. The S/PDIF Transmitter input data format in HW Mode is
always
LJ
and is independent of this setting. If the user desires I2S format PCM SDOUT data, the I/O
Header will have to be used.
Switch
Position
Function
M/S (Note 1.)
LO
LRCK and SCLK are inputs to CS53L21.
HI
LRCK and SCLK are outputs to CS53L21.
MCLKDIV2
LO
Internal MCLK to CS53L21 not divided.
HI
Internal MCLK to CS53L21 divided by 2.
I2S/LJ (Note 2.)
LO
CS53L21 Interface Format: Left-Justified.
HI
CS53L21 Interface Format: I²S.
Table 2. CS53L21 H/W Mode Control