Cirrus Logic CS5464 - Manual (Page 45)

CS5464
DS682F3 45
15. REVISION HISTORY
Revision Date Changes
T1 NOV 2005 Target Data Sheet
PP1 MAR 2006 Preliminary Release
PP2 JAN 2007 Update to correspond to rev C1 Silicon
F1 MAR 2007 Updated capitalization of register names for consistency with CS5467. Updated
Typical Connection diagram. Updated Phase Compensation Range from ±2.8° to
±5.4°. Updated document number to F1 for quality process level (QPL).
F2 JAN 2010 Increased on-chip reference temperature coefficient from 25 ppm / °C typ. to
40 ppm / °C typ.
F3 APR 2011 Removed lead-containing (Pb) device ordering information.