Cirrus Logic AN88 - Manual (Page 4)

AN88
4 AN88Rev2
MAXIMUM SCLK RATE
A machine cycle in the PIC16F84 consists 4 oscil-
lator periods or 400 ns if the microcontroller’s os-
cillator frequency is 10 MHz. Since the CS5525/6/
9’s maximum SCLK rate is 2MHz, additional no
operation (NOP) delays may be necessary to re-
duce the transfer rate if the microcontroller system
requires higher rate oscillators.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) developed for
Microchip’s controllers wasn’t designed to be as
flexible as the SPI port on Motorola’s 68HC05. To
get the Microchip’s SPI port to function with the
CS5525/6/9, the port needs to be initialized to idle
high, and the CS5525/6/9’s serial port needs to be
reset anytime information is transmitted between
the microcontroller and the converter.
DEVELOPMENT TOOL DESCRIPTION
The code in this application note was developed
using MPLAB
TM
, an integrated software
development package from Microchip, Inc.
Command Time
8 SCLKs
8 SCLKs Clear SDO Flag
Data SDO Continuous Conversion Read (PF bit = 1)
SDO
SCLK
SDI
t *
d
Data Time
24 SCLKs
MSB LSB
* td = XIN/OWR clock cycles for each conversion except the
first conversion which will take XIN/OWR + 7 clock cycles
XIN/OWR
Clock Cycles
Figure 5. Conversion/Acquisition Cycle with the PF Bit Asserted
MSB High-Byte
Mid-Byte
Low-Byte
A) 20-Bit Conversion Data Word
MSB High-Byte
Mid-Byte
Low-Byte
B) 16-Bit Conversion Data Word
0- always zero, 1 - always one,
OD - Oscillation Detect, OF - Overflow
Figure 6. Bit Representation/Storage in PIC16F84
D19 D18 D17 D16 D15 D14 D13 D12
D11 D10 D9 D8 D7 D6 D5 D4
D3 D2 D1 D0 0 0 OD OF
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 0 0 OD OF