Cirrus Logic AN89 - Manual (Page 10)

AN89
10 AN89Rev2
**************************************************************************************
* Routine - delay
* Input
- Count in register A
* Output - none
*
* This subroutine delays by using count from register A. The 68HC05
* development board uses a 4.0MHz clock (E = 2.0 MHz), thus each cycle is
* 500 nS. This delay is equivalent to (500ns)*(1545)*(count value),
* (a count of 720 provides a 556ms delay).
**************************************************************************************
delay
outlp
CLRX ; X used as inner loop count
innlp DECX ; 0-FF, FF-FE, FE-FD, ....1-0 256 loops
NOP ; 2 cycles
NOP ; 2 cycles
BNE innlp ; 10 cycles*256*500ns=1.28 ms
DECA ; Countdown the accumulator
BNE outlp ; 2569 cycles*500ns*A
RTS ; Exit subroutine
**************************************************************************************
* Interrupt Vectors
**************************************************************************************
NOT_USED RTI
ORG $1FF4 ; Interrupt Vectors
FDB NOT_USED ; SPI Interrupt
FDB NOT_USED ; SCI Interrupt
FDB NOT_USED ; Timer Interrupt
FDB NOT_USED ; IRQ Interrupt
FDB NOT_USED ; SWI Interrupt
FDB MAIN ; Reset interrupt- power on reset