Cirrus Logic AN89 - Manual (Page 4)

AN89
4 AN89Rev2
.MSB High-Byte
Mid-Byte
Low-Byte
A) 20-Bit Conversion Data Word
MSB High-Byte
Mid-Byte
Low-Byte
B) 16-Bit Conversion Data Word
0- always zero, 1 - always one,
OD - Oscillation Detect, OF - Overflow
Figure 6. Bit Representation/Storage in 68HC05
MAXIMUM SCLK RATE
A machine cycle in the 68HC05 consists 2 oscilla-
tor periods or 500 ns if the microcontroller’s oscil-
lator frequency is 4 MHz. Since the CS5525/6/9’s
maximum SCLK rate is 2MHz, additional no oper-
ation (NOP) delays may be necessary to reduce the
transfer rate if the microcontroller system requires
higher rate oscillators.
CONCLUSION
This application note presents an example of how
to interface the CS5525/6/9 to the 68HC05. It is di-
vided into two main sections: hardware and soft-
ware. The hardware section illustrates both a three-
wire and a four-wire interface. The three-wire in-
terface is SPI
TM
and MICROWIRE
TM
compatible.
The software section illustrates how to initialize the
converter and microcontroller, calibrate the con-
verters offset, write to and read from the ADC’s in-
ternal register, and acquire a conversion. The
software is modularized and illustrates important
subroutines, e.g. write_register and read_register.
The software described in this note is included in
the Appendix at the end of this document.
SPI
TM
is a trademark of Motorola.
MICROWIRE
TM
is a trademark of National Semi-
conductor.
D19 D18 D17 D16 D15 D14 D13 D12
D11 D10 D9 D8 D7 D6 D5 D4
D3 D2 D1 D0 0 0 OD OF
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 0 0 OD OF
Command Time
8 SCLKs
8 SCLKs Clear SDO Flag
Data SDO Continuous Conversion Read (PF bit = 1)
SDO
SCLK
SDI
t *
d
Data Time
24 SCLKs
MSB LSB
* td = XIN/OWR clock cycles for each conversion except the
first conversion which will take XIN/OWR + 7 clock cycles
XIN/OWR
Clock Cycles
Figure 5. Conversion/Acquisition Cycle with the PF Bit Asserted