CDB5571
16
DS768DB4
APPENDIX D. LAYER PLOTS
Figu
re 8.
To
p Silks
c
re
en
C
alibration
func
tion has been
removed from the
devic
e but
s
till appears on the
PCB. J2
mus
t be shorted
(grounded)
for
pro
p
er
op
era
tion. See App
end
ix
E for d
e
tails.
