Cirrus Logic CDB5571 - Manual (Page 8)

CDB5571
8 DS768DB4
3.4 Digital Section
3.4.1 Hardware Configuration
The CDB5571 evaluation board hardware comes pre-configured so the only connection required between
it and a data acquisition system is the serial port connection.
The hardware setup is reconfigurable through the hardware control interface connectors. Configure the
evaluation board by setting the appropriate control line to the appropriate logic level.
3.4.2 SPI™ Serial Port Communications
The CS5571 ADC communications port features an SPI™ serial port. It can be configured for SSC mode
(Master) or SEC mode (Slave) mode as shown in Table 4. Test points are provided to monitor serial com-
munications.
Connections to the serial interface are made according to the following table.
Table 4. Hardware Configuration Signals
Function Default Level Label Connector Test Point
Input Channel Select IN_A = Selected (Low) MUX J6, Pin 16 J3, Pin 2
Analog Input Buffers Buffers = Enabled (High) BUFEN J1 J3, Pin1
Serial Port Mode Sync. Self Clock = Enabled (High) SMODE J6, Pin 12 J3, Pin 3
Data Ready Flag Data Ready When Set (Low) RDY J8, Pin 10 J3, Pin 4
Reset Reset = Inactive (High) RST J6, Pin 6; S1 J3, Pin 6
Bipolar / Unipolar Mode Bipolar = Enabled (High) BP / UP J6, Pin 2 J3, Pin 8
Digital Filter Dither Dither = Enabled (High) DITHER J6, Pin 4 J3, Pin 9
Serial Port Communication Chip Select = Enabled (Low) CS J8, Pin 2 E23
Data Conversion Mode Continuous Conversion = Active (Low) CONV J8, Pin 12 E21
Table 5. Serial Interface Connections
Function Label Connector Test Point
Chip Select CS J8, Pin 2 E23
Serial Data Input SDI J8, Pin 4 E24
Serial Data Output SDO J8, Pin 6 E25
Serial Clock SCLK J8, Pin 8 E26