Cirrus Logic CS61583 User Manual

Page 36

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reset can be used to initialize the control logic.
Both channels are powered up after exiting reset.

TRANSMIT CIRCUIT

The transmit clock and data signals are supplied
on BNC inputs labeled TCLK(1,2), TPOS(1,2),
and TNEG(1,2). When the coder mode is
disabled, data is supplied on the TPOS(1,2) and
TNEG(1,2) BNC inputs in RZ format. When the
coder mode enabled, data is supplied on the
TDATA(1,2) BNC input in NRZ format and the
TNEG(1,2) BNC input may be used to indicate
the AIS alarm condition as described in the
Board Configuration section.

The transmitter output is transformer coupled to
the line interface through 1:1.15 step-up
transformers T1 and T4. The signal is available
at either the TTIP(1,2) and TRING(1,2) binding
posts or the TX(1,2) bantam jacks.

Capacitors C2 and C11 prevent output stage
imbalances from producing a DC current that
may saturate the transformer and result in an
output level offset. Capacitors C1 and C12
provide transmitter return loss and are socketed
so the value may be changed according to the
application. A 220 pF capacitor is required for
100

Ω

twisted-pair T1 or 120

Ω

twisted-pair E1

applications. A 470 pF capacitor is required for
75

Ω

coax E1 applications. These capacitors are

included with the evaluation board.

Optional diode locations D6-D9 and D10-D13
and optional resistor locations R8-R9 and
R18-R19 provide test locations to evaluate
transmit line interface protection circuitry.

RECEIVE CIRCUIT

The receive signal is input at either the
RTIP(1,2) and RRING(1,2) binding posts or the
RX(1,2) bantam jacks. The receive signal is

transformer coupled to the CS61583 through
1:1.15 step-down transformers T2 and T3.

The receive line is terminated by resistors R3-R4
and R14-R15 to provide impedance matching
and receiver return loss. They are socketed so
the values may be changed according to the
application. The evaluation board is supplied
from the factory with 38.3

Ω

resistors for

terminating

100Ω

twisted-pair T1 lines, 45.3

Ω

resistors for terminating 120

Ω

twisted-pair E1

lines, and 28.7

Ω

resistors

for terminating 75

Ω

coaxial E1 lines. Capacitors C4 and C10 provide
a differential input voltage reference.

Optional resistor locations R1-R2, R12-R13,
R16-R17, and R24-R25 provide test locations to
evaluate receive line interface protection
circuitry.

The recovered clock and data signals are
available on BNC outputs labeled RCLK(1,2),
RPOS(1,2), and RNEG(1,2). When the coder
mode is disabled, data is available on the
RPOS(1,2) and RNEG(1,2) BNC outputs in RZ
format. When the coder mode is enabled, data is
available on the RDATA(1,2) BNC output in
NRZ format and bipolar violations are reported
on BPV(1,2).

REFERENCE CLOCK

The CDB61583 requires a T1 or E1 reference
clock for operation. This clock may operate at
either a 1-X rate (1.544 MHz or 2.048 MHz) or
an 8-X rate (12.352 MHz or 16.384 MHz) and
can be supplied by either a crystal oscillator or
an external reference. The evaluation board is
supplied from the factory with two crystal
oscillators for T1 and E1 operation.

CDB61583

DB172PP1

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