Cirrus Logic CS8427 - Manual (Page 28)

CS8427
28 DS477F5
11. CONTROL PORT REGISTER BIT DEFINITIONS
11.1 Control 1 (01h)
SWCLK - Controls output of OMCK on RMCK when PLL loses lock
Default = ‘0’
0 - RMCK default function
1 - OMCK output on RMCK pin
VSET - Transmitted Validity bit level
Default = ‘0’
0 - Indicates data is valid, linear PCM audio data
1 - Indicates data is invalid or not linear PCM audio data
MUTESAO - Mute control for the serial audio output port
Default = ‘0’
0 - Not Muted
1 - Muted
MUTEAES - Mute control for the AES transmitter output
Default = ‘0’
0 - Not Muted
1 - Muted
INT1:INT0 - Interrupt output pin (INT) control
Default = ‘00’
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull up resistor on the INT pin.
11 - Reserved
TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier
Default = ‘0’
0 - TCBL is an input
1 - TCBL is an output
11.2 Control 2 (02h)
HOLD1:HOLD0 - Determine how received audio sample is affected when a receiver error occurs
Default = ‘00’
00 - Hold the last valid audio sample
01 - Replace the current audio sample with 00 (mute)
10 - Do not change the received audio sample
11 - Reserved
RMCKF - Select recovered master clock output pin frequency.
Default = ‘0’
0 - RMCK is equal to 256 * Fsi
1 - RMCK is equal to 128 * Fsi
7 6 5 4 3 2 1 0
SWCLK VSET MUTESAO MUTEAES 0 INT1 INT0 TCBLD
7 6 5 4 3 2 1 0
0 HOLD1 HOLD0 RMCKF MMR MMT MMTCS MMTLR