3 locking to the ilrck input, 4 jitter tolerance, Figure 32. jitter tolerance template – Cirrus Logic CS8427 User Manual
Page 58: Table 8. locking to the ilrck input, D table 8, the compon, Nd table 8, Cs8427
CS8427
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DS477F5
20.3.3 Locking to the ILRCK Input
CS8427 parts that are configured to lock to the IL-
RCK input should use the external PLL component
values listed in Table 8. Note that parts that need
to lock to both ILRCK and RXP/RXN should use
these values. Values listed for the 32 to 96 kHz Fs
range will have the highest corner frequency jitter
attenuation curve, take the shortest time to lock,
and offer the best output jitter performance.
20.3.4 Jitter Tolerance
Shown in Figure 32 is the Receiver Jitter Tolerance
template as illustrated in the AES3 and IEC60958-
4 specification. CS8427 parts used with the appro-
priate external PLL component values (as noted in
Table 7) have been tested to pass this template.
Revision
Fs Range
(kHz)
R
FILT
(k
Ω) C
FILT
(
μF) C
RIP
(nF) PLL Lock Time (ms)
A
8 to 96
1.3
2.7
62
120
A
32-96
5.1
0.15
3.9
70
A1/A2
8 to 96
0.3
1.0
100
120
A1/A2
32-96
0.6
0.22
22
70
Table 8. Locking to the ILRCK Input
Figure 32. Jitter Tolerance Template