Switching waveforms – Cypress CY7C0251AV User Manual
Page 13
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J
Page 13 of 19
Notes
43. CE = HIGH for the duration of the above timing (both write and read cycle).
44. IO
0R
= IO
0L
= LOW (request semaphore); CE
R
= CE
L
= HIGH.
45. Semaphores are reset (available to both ports) at cycle start.
46. If t
SPS
is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Switching Waveforms
(continued)
t
SOP
t
SAA
VALID ADRESS
VALID ADRESS
t
HD
DATA
IN
VALID
DATA
OUT
VALID
t
OHA
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE
READ CYCLE
OE
R/W
IO
0
SEM
A
0
–A
2
Figure 10. Semaphore Read After Write Timing, Either Side
[43]
MATCH
t
SPS
A
0L
–A
2L
MATCH
R/W
L
SEM
L
A
0R
–A
2R
R/W
R
SEM
R
Figure 11. Timing Diagram of Semaphore Contention