Cypress CY7C0251AV - Manual (Page 15)

CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 15 of 19
Note
48. If t
PS
is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
Switching Waveforms (continued)
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
CE
R
Valid First:
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
Figure 14. Busy Timing Diagram No.1 (CE Arbitration)
[48]
CE
L
Valid First
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Right Address Valid First:
Figure 15. Busy Timing Diagram No.2 (Address Arbitration)
[48]
Left Address Valid First:
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