Dell Broadcom NetXtreme Family of Adapters User Manual
Page 158
User Diagnostics: Broadcom Broadcom NetXtreme BCM57XX User Guide
file:///C|/Users/Nalina_N_S/Documents/NetXtreme/English/dosdiag.htm[9/5/2014 3:32:22 PM]
B1
Scratch Pad
Walking bit. For each address, data one is written and read back for testing. Then it shifts the
data left one bit, so the data becomes two and repeats the same test. It repeats the test 32 times
until the test bit is shifted out of the test address. The same test is repeated for entire test range.
Pseudo-Random Data. A precalculated pseudo-random data set is used to write unique data to
each test RAM. After passing the test, the program reads back the data one more time to ensure
that the data is still correct.
Data Read/Write Test: This test writes test data to the SRAM and reads it back to ensure that
the data is correct. The test data used is 0x00000000, 0xFFFFFFFF, 0xAA55AA55, and 0x55AA55AA.
Alternate Data Pattern Test. This test writes test data into the SRAM, writes complement test
data to the next address, and reads back both to ensure the data is correct. After the test, the
program reads back data one more time to ensure that the data is still correct. The test data used
is 0x00000000, 0xFFFFFFFF, 0xAA55AA55, and 0x55AA55AA.
B2
BD SRAM
This test tests the Buffer Descriptor (BD) SRAM. This test performs in the same way as the Scratch
Pad Test described in B1.
B3
DMA SRAM
This test tests the direct memory access (DMA) SRAM by performing the Scratch Pad Test described
in test B1.
B4
MBUF SRAM
This test tests the memory access buffer (MBUF) SRAM by performing the Scratch Pad Test
described in test B1.
B5
MBUF SRAM
via DMA
This test uses 8 data test patterns. A 0x1000-sized data buffer is used for this test. Before each
pattern test, the buffer is initialized and filled with the test pattern. It then performs a 0x1000-sized
transmit DMA from the host buffer to the adapter MBUF memory.
The test verifies the data integrity in the adapter MBUF memory against the host memory and
repeats the DMA for the entire MBUF buffer. Then, the test performs a receive DMA from the
adapter to the host. The 0x1000-byte test buffer is cleared to 0 before each receive DMA. After the
test verifies the integrity of the data, the test is repeated for the entire MBUF SRAM range. The 8
test patterns are described below.
Test Pattern Description
16 00s and 16 FF's Fills the entire host DMA buffer with 16 bytes of 00s and then
16 bytes of FF's.
16 FF's and 16 00s Fills the entire host DMA buffer with 16 bytes of FF's and then
16 bytes of 00s.
32 00s and 32 FF's Fills the entire host DMA buffer with 32 bytes of 00s and then
32 bytes of FF's.
32 FF's and 32 00s Fills the entire host DMA buffer with 32 bytes of FF's and then
32 bytes of 00s.
00000000 Fills the entire host DMA buffer with all 00s.
FFFFFFFF Fills the entire host DMA buffer with all FF's.
AA55AA55 Fills the entire host DMA buffer with data 0xAA55AA55.
55AA55AA Fills the entire host DMA buffer with data 0x55AA55AA.
B7
CPU GPR
This test tests the CPU General Purpose registers and performs in the same way as the Scratch Pad
Test (B1) over 3 different voltages (1.1V, 1.2V, and 1.3V).
Group C: Miscellaneous Tests
C1
NVRAM
Incremental test data is used in the electrically erasable programmable read-only memory
(EEPROM) test. The test fills the test range with test data and reads the data back to verify the
content. Afterwards, the test fills the test range with 0s to clear the memory.
C2
CPU
This test opens the Cpu.bin file. If the file exists and content is good, the test loads code to the RX
CPU and TX CPU and verifies the CPU execution.
C3
DMA
This test tests both high-priority direct memory access (DMA) and low-priority DMA. The test moves
data from the host memory to the adapter SRAM and verifies the data. The test then moves data
back to the host memory to again verify the data.
C4
MII
The medium independent interface (MII) test function is identical to that of the Control Register
Test (A2). Each register specified in the configuration contents defines the read-only and read/write
bits. The test writes 0s and 1s to the test bits to ensure that the read-only bit values are not
changed and that the read/write bits are changed.
The test attempts to read the register configuration file (Miireg.txt) for the register definitions. If the
file does not exist, the following table is used:
Offset Read-Only Mask Read/Write Mask
0x00 0x0000 0x7180
0x02 0xFFFF 0x0000
0x03 0xFFFF 0x0000
0x04 0x0000 0xFFFF
0x05 0xEFFF 0x0000
0x06 0x0001 0x0000
0x07 0x0800 0xB7FF
0x08 0xFFFF 0x0000
0x09 0x0000 0xFF00
0x0A 0x7C00 0x0000
0x10 0x0000 0xFFBF
0x11 0x7C00 0x0000
0x19 0x7C00 0x0000
0x1E 0x0000 0xFFFF
0x1F 0x0000 0xFFFF