Cypress SL811HS - Manual (Page 28)

SL811HS
Document 38-08008 Rev. *D Page 28 of 32
DMA Write Cycle
Note nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence is not implemented as requested, the
next nDRQ is not inserted.
Parameter Description Min. Typ. Max.
tdack nDACK low 80 ns
tdwrlo nDACK to nWR low delay 5 ns
tdakrq nDACK low to nDRQ high delay 5 ns
tdwrp nWR pulse width 65 ns
tdhld Data hold after nWR high 5 ns
tdsu Data set-up to nWR strobe low 60 ns
tackrq NDACK high to nDRQ low 5 ns
tackwrh NDACK high to nDRQ low 5 ns
twrcycle DMA Write Cycle Time 150 ns
n D R Q
n D A C K
D 0-D 7 D A T A
n W R
S L 811 D M A W R IT E C Y C L E T IM IN G
tdw rp tdsu
tdack
tdhld
tdw rlo
tackw rh
tdakrq
tackrq
DMA Write Cycle