Kontron AT8404 - Manual (Page 19)

Introduction
6 AT8404 User Guide
www.kontron.com
1.2 Technical Specification
Table 1-2: AT8404 Main Specifications
AT8404 SPECIFICATIONS
U
nit C
om
puter and Me
mor
y
PowerPC IBM PPC 405
GPr-400MHz
• IBM PowerPC ® 405 32-bit RISC processor core operating up to 400MHz with 16KB I-
and D-caches
• PC-133 synchronus DRAM (SDRAM) interface
• 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications
• 4KB on-chip memory (OCM)
• DMA support for external peripherals, internal UART and memory
• Scatter-gather chaining supported
• Four channels
• PCI Revision 2.2 compliant interface (32-bit, up to 66MHz)
• Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII)
• Two serial ports (16550 compatible UART)
• Internal processor local Bus (PLB) runs at SDRAM interface frequency
• IEEE 1149.1 (JTAG) boundary scan
Et
her
ne
t
Broadcom 5466R
• Advanced power management Line-side and MAC-side loopback
• Ethernet@WireSpeed
• Cable plant diagnostics that detects cable plant impairments
• Automatic detection and correction of wiring pair swaps, pair skew, and pair polarity
• Robust CESD tolerance and low EMI emissions
• Support for jumbo packets up to 10 KB in size
• IEEE 1149.1 (JTAG) boundary scan
Et
her
ne
t
Broadcom 56502
• 24 10/100/1000 Mbps Ethernet ports
• 2 10GbE ports
• Fifth generation of StrataSwitch and StrataXGS product line
• Line-rate switching for all packet sizes and conditions
• On-chip data packet memory and table memory
• Advanced Fast Filter Processor (FFP) Content Aware classification
• Advanced security features in hardware
• Port-trunking and mirroring supported across stack
• Advanced packet flow control:
• Head-of-line-blocking prevention
• Back pressure support
• QoS queues per port with hierarchical minimum/maximum shaping per class of Ser-
vice (CoS) per queue per port
• Standard compliant 802.1ad provider bridging
• IEEE 1149.1 (JTAG) boundary scan